1. Field of the Invention
The present invention relates generally to stereolithography and, more specifically, to the use of stereolithography to fabricate structures on, or components of, semiconductor testing apparatus and to the resulting structures.
2. State of the Art
In the past decade, a manufacturing technique termed xe2x80x9cstereolithographyxe2x80x9d, also known as xe2x80x9clayered manufacturingxe2x80x9d, has evolved to a degree where it is employed in many industries.
Essentially, stereolithography, as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or xe2x80x9cslicedxe2x80x9d into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object. Surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries. This is followed by selective consolidation or fixation of the material to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form and the material itself may be consolidated, fixed or cured, or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size. When a liquid is employed, resolution is highly dependent upon the minimum surface area of the liquid which can be fixed (cured) and the minimum thickness of a layer which can be generated given the viscosity of the liquid and other parameters such as transparency to radiation or particle bombardment (see below) used to effect at least a partial cure of the liquid to a structurally stable state. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography enabled rapid fabrication of molds and prototypes of objects from CAD flies. Thus, either male or female forms on which mold material might be disposed could be rapidly generated. Prototypes of objects could be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques.
However, to the inventor""s knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results are required.
In the electronics industry, computer chips are typically manufactured by configuring a large number of integrated circuits on a wafer and subdividing the wafer to form singulated devices or dice. Such dice, including so-called xe2x80x9cflip-chipxe2x80x9d dice, have xe2x80x9csolder bumpsxe2x80x9d or other conductors, or conductive structures, for electrically connecting each die to circuitry external thereto. These conductors are also useful for temporary connection of a die to a test circuit to determine its fitness for the intended use. Tests may be conducted before or after the die has been packaged.
One type of conventional test apparatus that is used to test the electrical characteristics of semiconductor devices includes a carrier substrate, a test substrate positioned on the carrier substrate, and a fence disposed over the test substrate. The carrier substrate includes terminals and electrical traces that lead from the terminals to communicate with test equipment. Terminals of the carrier substrate are wire bonded to contact pads on the test substrate. The contact pads of the test substrate communicate with test pads thereof. The test pads are arranged to correspond to a pattern of conductors, such as solder balls, conductive pillars, bond pads, or other conductive structures of a semiconductor device to be tested. The fence forms an aperture over the test substrate to facilitate alignment of the semiconductor device to be tested relative to the substrate. As a die to be tested is aligned with a test substrate, test pads of the test substrate temporarily mate or contact the conductors of the semiconductor device. Such test apparatus can be configured to test bare or minimally packaged semiconductor dice or packaged semiconductor devices, such as ball grid array (BGA) packages and chip-scale packages (CSPs).
Conventionally, the bond wires of a test apparatus have been covered with a silicone gel or a nonconductive epoxy xe2x80x9cglob-topxe2x80x9d material. As such materials can flow, the use of such materials typically also requires that external fences or walls be used to contain such materials in the desired locations. Internal fences or walls may also be required to prevent such glob top, silicone, and other materials from flowing onto the test pads of a test substrate, which can prevent the electrical connection of tested semiconductor devices to the test substrate. Otherwise, if flowable materials are used to cover wire bonds, these materials may have to be removed from the test pads or from the conductors of the tested semiconductor device to ensure adequate electrical connections between the test substrate and the semiconductor device assembled therewith.
In other test apparatus, a photoresist material is used to cover the bond wires that connect a test substrate to a carrier substrate. When photoresist materials are used to protect bond wires, the use of a mask and several exposure and developing steps are required.
Accordingly, there is a need for a method of efficiently and effectively protecting the bond wires of semiconductor device test apparatus, as well as protective structures and test apparatus formed by such a method.
The present invention includes a method of fabricating a protective structure over the bond wires of a semiconductor device assembly, such as the bond wires of the semiconductor device test apparatus that connect test pads of a test substrate to a carrier substrate and, thereby, to the semiconductor device test apparatus. The present invention also semiconductor device assemblies so formed.
A test apparatus embodying teachings of the present invention includes a silicon or other known test substrate with test pads on a surface thereof for receiving complementarily arranged conductors, or conductive structures, of a semiconductor device and electrical traces leading from the test pads to peripheral portions of the test substrate. The test pads may be substantially flush with the surface of the test substrate, recessed relative to the surface, or protrude from the surface, depending upon the types of conductors on the semiconductor devices to be tested with the test substrate or upon the configurations of components of the test apparatus that overlie the test substrate.
The test substrate is secured to a carrier substrate and electrical connections are formed between terminals of the carrier substrate and the traces and test pads of the test substrate. Preferably, bond wires are used to establish the electrical connections between the electrical traces of the test substrate and their corresponding terminals of the carrier substrate. The terminals of the carrier substrate are configured to communicate with known semiconductor device testing equipment.
The test apparatus also has protective structures located over the bond wires. The structures formed in accordance with teachings of the present invention may be used to physically protect, seal, and isolate the bond wires of a test apparatus so as to prevent physical damage to and shorting of the bond wires.
A so-called xe2x80x9cfence,xe2x80x9d which has a large opening therethrough, is positioned over the test substrate. The fence and the opening therethrough are configured to seat a semiconductor device face down over the test substrate, aligning the conductors on the semiconductor device with their corresponding test pads of the test substrate. The opening through the fence may substantially expose a contact surface of the test substrate. The opening through the fence may have a plurality of vertically extending slots spaced about the periphery thereof, which provide additional tolerances at the periphery of the opening to facilitate the insertion of semiconductor devices into, and their removal from, the fence.
As another alternative, the fence or the protective structure may include a relatively thin layer that is positionable over the test substrate so as to protect the test substrate from damage during the repeated testing of semiconductor devices. Apertures formed through the thin protective layer of the fence over at least test pads of the test substrate allow for contact between the test pads and corresponding conductors of a die to be tested and may be used to facilitate alignment of the semiconductor device relative to the test substrate.
The present invention employs computer-controlled, 3-D computer-assisted drafting (CAD) initiated, stereolithographic techniques to rapidly form precision layers of material to specific surfaces of a test substrate and carrier substrate of a test apparatus.
In the stereolithographic processes that are useful in the present invention, one or more layers of a photo-curable liquid, referred to herein as a photopolymer, are sequentially placed on or laterally adjacent to the item to be covered, and the liquid photopolymer of each layer is cured to at least a semisolid state by a precisely directed beam of laser radiation at substantially ambient temperature. Multiple superimposed, contiguous, mutually adhered layers, each separately cured, form one or more precision three-dimensional structures of desired dimensions.
For example, a substrate may be covered with a layer of liquid polyimide or other photopolymer which is cured only in particular locations to an at least semisolid state by precisely directed laser radiation at a substantially ambient temperature. As the regions of the layer that are cured by the laser may be selected, photopolymer located over certain regions of the substrate, such as the contact pads thereof, may be left uncured. Thus, apertures may be formed through the protective layer substantially simultaneously with formation of solid regions of a structure. A single layer having a uniform thickness of, for example, about 25 xcexcm (1 mil) may be formed on the surface of the wafer. Single layers having thicknesses of up to about 10 mil or more may be formed, the maximum possible thickness of each layer being limited only by the maximum depth into the liquid photopolymer that the laser beam can penetrate. Multiple superimposed layers, each separately cured, may be formed to create structure layers of even greater thickness while maintaining a thickness accuracy not achievable by conventional techniques.
In one embodiment of the method, the bond wire protectors and the fence are fabricated on a substrate using precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser to fix or cure a liquid material in the form of a photopolymer. However, the invention is not so limited and other stereolithographically applicable materials may be employed in the present invention. The apparatus used in the present invention may also incorporate a machine vision system to locate substrates and features on the substrates, such as bond wires and test pads. The method of the present invention encompasses the use of all stereolithographic apparatus and the application of any and all materials thereby, including both metallic and nonmetallic materials applied in any state and cured or otherwise fixed to at least a semisolid state to define a three-dimensional layer or layers having identifiable boundaries.
The highly precise stereolithographic process provides accurate alignment of the conductors of a semiconductor device to be tested with the test pads of the test substrate, providing good electrical connection without bump deformation.
The bond wire protectors and the fence may be fabricated separately by use of individual CAD programs. In another embodiment, the fence is formed stereolithographically to be integral with the bond wire protectors.
Alternatively, a fence can be fabricated on the test and carrier substrates by other known processes or fabricated separately from the test apparatus by known processes and subsequently assembled with the test substrate and carrier substrate assembly. As another alternative, a stereolithographically formed fence can be formed separately from the remainder of the test apparatus and then assembled therewith.
Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.